1. Technical Field
The present invention relates generally to one-chip microcomputers and more particularly to a one-chip microcomputer with improved processing speed when a data exchange is made between a group of internal registers and RAM, an I/O buffer or the like.
2. Background Art
One-chip microcomputers are widely used as control circuits in cameras, home electric appliances, and other kinds of electronic equipment, these being generally 4- or 8-bit one-chip microcomputers. A one-chip microcomputer of this sort is slightly different in internal construction from a general purpose microprocessor in that RAM and the like, each having a fixed capacity, are contained in one chip and connected to an internal bus. An exchange of signals with an external device is made via an I/O buffer connected to the internal bus. Such a one-chip microcomputer is designed to exchange data with an external circuit via the I/O buffer under the control of a central processor (or a controller, these are hereinafter collectively called `CPU`) over these circuits.
The one-chip microcomputer incorporates various kinds of commands different from those associated with the general purpose microprocessor to exercise control efficiently. Among these commands, there is one (a data exchange command) for instructing the group of registers within CPU and CPU to exchange data via the internal bus with RAM and the I/O buffer as external circuits.
Data exchange processing methods during the execution of a data exchange command from the conventional one-chip microcomputer are as follows:
A first method, as shown in FIG. 3(a), is to transfer two kinds of data 11 (e.g., the data held in the internal register) and 12 (e.g., the data held in RAM or the I/O buffer) in one machine cycle successively to a data bus on a time-sharing basis. A second method is, as shown in FIG. 3(b), to transfer data 11, 12 from one side to the other in respective machine cycles. As two machine cycles are employed in this later method, the timing of transferring data from CPU (internal register) to RAM or the I/O buffer and that of transferring data to CPU may be allotted to different machine cycles. As a result, it becomes possible to divide the data transfer direction in accordance with the machine cycles. In this case, however, two machine cycle periods will be required for such data exchange as shown in FIG. 3(b). Incidentally, the last period 13 in each machine cycle is a precharged second with respect to the bus.
The first method for data exchange processing makes it possible to implement the data exchange processing in one machine cycle. However, data transfer timing on a bus has to be controlled on a time-sharing basis as sequential data transfer from one to another, that is, between RAM or the I/O buffer and the internal register as objects for data exchange, is needed in response to a limited number of clock pulses within one machine cycle. The disadvantage is that control of data transfer becomes complicated. The second method is also disadvantageous as instruction execution takes time as two machine cycles are required. Moreover, a number of data exchange commands are used in such a one-chip microcomputer and this tends to lower the total processing speed.